Wires on a chip

On a chip, a net is a set of pins that all need to be connected to the same signal. The router lays metal wires connecting them, often choosing intermediate via points to keep total wire length short and avoid blocked regions. That is rectilinear Steiner tree on a grid graph. Cadence Innovus and Synopsys IC Compiler run Steiner-tree solvers as inner loops, optimizing total wirelength across millions of nets per chip. The same problem runs in multicast routing — IP multicast trees are Steiner trees on the network graph, with routers as potential Steiner points — and in fiber buildout planning, where ISPs decide which streets to trench given which neighborhoods they have to reach.