Reducibility
Glossary Contents
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Chapter I Satisfiability
Ch II →
  1. 01 — The mother problem
  2. 02 — DPLL in Prolog
  3. 03 — Why chip companies care
03

Why chip companies care

A SAT solver is the safety net between an HDL change and a billion-dollar mask set.

In 1994 Intel shipped a Pentium with a faulty floating-point divider. The Pentium FDIV bug recall cost roughly $475 million in 1994 dollars — about $1.05 billion in 2026 USD after CPI adjustment — and is the textbook reason hardware verification matters. Today, before silicon goes to a fab, designers run equivalence checking: does this gate-level netlist compute the same function as the RTL spec? That question is encoded as a SAT instance — millions of clauses, hundreds of thousands of variables — and fed to industrial solvers descended from MiniSat: Glucose, CaDiCaL, Kissat. Cadence Conformal, Synopsys Formality, and OneSpin are SAT solvers wearing EDA suits. A modern mask set runs $5–30M (2026 USD) for typical nodes and well into nine figures at the leading edge; you want SAT to say UNSAT before you tape out.

In plain terms

Chip designers write what the chip should do (a spec) and what the chip will do (a circuit). A SAT solver checks whether the two ever disagree on any input. If even one disagreeing input exists, the design goes back to the drawing board — much cheaper than discovering it after manufacturing.

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End of Chapter I
Chapter II 0-1 Integer Programming →
← 02 DPLL in Prolog
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04 Booleans in disguise →